DBUSYF=IDLE, DSTART=LIMIT, CLKSEL=APB, DPTR=LIMIT, STDOSEL=NO_DIFF, HDOSEL=THREE_DIFF, DEND=LIMIT
Module Operating Mode
| CLKDIV | Input Clock Divider. |
| CLKSEL | Input Clock (F 0 (APB): Set the APB as the input clock (FCLKIN). 1 (TIMER0): Set Timer 0 low overflows divided by 2 as the input clock (FCLKIN). 2 (HL_ECI): Set high-to-low transitions on ECI divided by 2 as the input clock (FCLKIN). 3 (EXTOSCN): Set the external oscillator module output (EXTOSCn) divided by 2 as the input clock (FCLKIN). 4 (ECI): Set ECI transitions divided by 2 as the input clock (FCLKIN). |
| HDOSEL | High Drive Port Bank Output Select. 0 (THREE_DIFF): Select three differential outputs from Channels 3, 4, and 5 for the High Drive pins. 1 (TWO_DIFF): Select the differential outputs from Channels 4 and 5 and non-differential outputs from Channels 2 and 3 for the High Drive pins. 2 (ONE_DIFF): Select the differential output from Channel 5 and non-differential outputs from Channels 1-4 for the High Drive pins. 3 (NO_DIFF): Select the non-differential channel outputs (Channels 0-5) for the High Drive pins. |
| DEND | DMA Write End Index. 0 (LIMIT): Set the last register in a DMA write transfer to LIMITUPD. 1 (CH0): Set the last register in a DMA write transfer to Channel 0 CCAPVUPD. 2 (CH1): Set the last register in a DMA write transfer to Channel 1 CCAPVUPD. 3 (CH2): Set the last register in a DMA write transfer to Channel 2 CCAPVUPD. 4 (CH3): Set the last register in a DMA write transfer to Channel 3 CCAPVUPD. 5 (CH4): Set the last register in a DMA write transfer to Channel 4 CCAPVUPD. 6 (CH5): Set the last register in a DMA write transfer to Channel 5 CCAPVUPD. 7 (EMPTY): Empty slot. |
| DPTR | DMA Write Transfer Pointer. 0 (LIMIT): The DMA channel will write to LIMITUPD next. 1 (CH0): The DMA channel will write to Channel 0 CCAPVUPD next. 2 (CH1): The DMA channel will write to Channel 1 CCAPVUPD next. 3 (CH2): The DMA channel will write to Channel 2 CCAPVUPD next. 4 (CH3): The DMA channel will write to Channel 3 CCAPVUPD next. 5 (CH4): The DMA channel will write to Channel 4 CCAPVUPD next. 6 (CH5): The DMA channel will write to Channel 5 CCAPVUPD next. 7 (EMPTY): Empty slot. |
| DSTART | DMA Target Start Index. 0 (LIMIT): Set the first register in a DMA write transfer to LIMITUPD. 1 (CH0): Set the first register in a DMA write transfer to Channel 0 CCAPVUPD. 2 (CH1): Set the first register in a DMA write transfer to Channel 1 CCAPVUPD. 3 (CH2): Set the first register in a DMA write transfer to Channel 2 CCAPVUPD. 4 (CH3): Set the first register in a DMA write transfer to Channel 3 CCAPVUPD. 5 (CH4): Set the first register in a DMA write transfer to Channel 4 CCAPVUPD. 6 (CH5): Set the first register in a DMA write transfer to Channel 5 CCAPVUPD. 7 (EMPTY): Empty slot. |
| DBUSYF | DMA Busy Flag. 0 (IDLE): The DMA channel is not servicing an EPCA control transfer. 1 (BUSY): The DMA channel is busy servicing an EPCA control transfer. |
| STDOSEL | Standard Port Bank Output Select. 0 (NO_DIFF): Select the non-differential channel outputs (Channels 0-5) for the standard PB pins. 1 (ONE_DIFF): Select the differential output from Channel 2 and non-differential outputs from Channels 0, 1, 3, and 4 for the standard PB pins. 2 (TWO_DIFF): Select the differential outputs from Channels 1 and 2 and non-differential outputs from Channels 0 and 3 for the standard PB pins. 3 (THREE_DIFF): Select three differential outputs from Channels 0, 1, and 2 for the standard PB pins. |